pcbx.tools

What to upload

Export the source board document from EasyEDA. Preserve the Standard or Pro document structure; a screenshot or PDF drawing cannot replace a board file.

What to review

Check the detected document variant, polygon pads, bottom-side footprints and layers. Standard and Pro do not have identical supported subsets.

Conversion outputs

These routes depend on supported source contents. Each upload receives its own result and notes. Shared editor engine for supported board and authored schematic profiles. Coverage and independent qualification are reported separately.

Unavailable output options (22)
  • gEDA PCBIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • CADSTAR PCB ArchiveIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Horizon EDA boardIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Cadence Allegro (Specctra DSN exchange)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • OrCAD Capture (Specctra DSN exchange)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Specctra DSNIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Siemens Xpedition (IDF exchange)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • PADS Logic ASCIIIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • ViewDraw text schematicIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • HyperLynx HYPIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Concept HDL / Design Entry HDL (Concept HDL CPM/CSA)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Allegro text netlistIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • EDIFIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • IDF 3.0 board outline and drillingIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • LibrePCB projectIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • GenCADIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • BREP (Open CASCADE BREP)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • PLY polygon meshIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • KiCad XML netlist (KiCad S-expression netlist)In development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • KiCad synthesized connectivity schematicIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • Component BOM CSVIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

  • LTspice ASCIn development · Unavailable

    The source remains in scope. This shared-engine route is not available yet.

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